A company is looking for a Senior Verification Engineer.
Key Responsibilities
Develop verification and simulation strategies, conduct design reviews, and create digital test plans
Construct and maintain simulation environments using System Verilog with UVM and perform regression tests
Lead a team of verification engineers to ensure full verification of complex devices
Required Qualifications
Bachelor's degree in Electrical Engineering or Computer Science; Master's degree preferred
A minimum of 10 years of verification engineering experience
Experience with simulation tools such as Mentor Graphics Modelsim / Questasim
Ability to analyze Verilog RTL and diagnose test failures
US Citizenship required
