Job Summary
We are seeking an experienced Design-for-Test (DFT) Contractor to support the testing and validation of next-generation semiconductor SoCs. This role will work closely with Front-End and Physical Design teams to implement robust DFT and test solutions, directly contributing to RF and Bluetooth/Wireless LAN product lines.
Key Responsibilities
• Design, implement, and validate DFT architectures for advanced SoC designs
• Develop, debug, and optimize Memory BIST using Siemens Tessent flows
• Perform gate-level simulations and resolve simulation issues
• Create and maintain automation scripts using Tcl, Perl, and Python
• Implement scan compression techniques (SEQ, Ultra, TestKompress)
• Generate ATPG patterns using Tetramax
• Support ATPG diagnosis, ATE debug, and silicon bring-up activities
• Perform DFT pattern translation using VTRAN
• Work with RTL designs using Verilog/SystemVerilog
• Apply basic STA and timing analysis concepts using PrimeTime, including:
• CDC checks
• Clock gating
• Timing constraints
Required Skills & Experience
• 5+ years of hands-on industry experience in Design-for-Test (DFT)
• Strong analytical, problem-solving, and debugging skills
• Proven ability to work independently and deliver high-quality results with minimal supervision
