About the position
Utility Computing (UC)
AWS Utility Computing (UC) provides product innovations — from foundational
services such as Amazon’s Simple Storage Service (S3) and Amazon Elastic Compute
Cloud (EC2), to consistently released new product innovations that continue to
set AWS’s services and features apart in the industry. As a member of the UC
organization, you’ll support the development and management of Compute,
Database, Storage, Internet of Things (Iot), Platform, and Productivity Apps
services in AWS, including support for customers who require specialized
security solutions for customers who require specialized security solutions for
their cloud services.
Annapurna Labs (our organization within AWS UC) designs silicon and software
that accelerates innovation. Customers choose us to create cloud solutions that
solve challenges that were unimaginable a short time ago—even yesterday. Our
custom chips, accelerators, and software stacks enable us to take on technical
challenges that have never been seen before, and deliver results that help our
customers change the world.
About AWS
Amazon Web Services (AWS) is the world’s most comprehensive and broadly adopted
cloud platform. We pioneered cloud computing and never stopped innovating —
that’s why customers from the most successful startups to Global 500 companies
trust our robust suite of products and services to power their businesses.
Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers.
As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be
responsible for the design and optimization of hardware in our data centers
including AWS Inferentia, our custom designed machine learning inference
datacenter server. Our success depends on our world-class server infrastructure;
we’re handling massive scale and rapid integration of emergent technologies.
We’re looking for an ASIC Design Eengineer to help us trail-blaze new
technologies and architectures, while ensuring high design quality and making
the right trade-offs.
Responsibilities
• integrate multiple subsystems into top level SOC, ensure correct
clock/reset/functional/DFT signal routing
• As a key member of the ASIC design team, you will implement and deliver high
performance, area and power efficient RTL to achieve design targets and
specifications.
• Analyze design, microarchitecture or architecture to make trade-offs based on
features, power, performance or area requirements.
• Develop micro-architecture, implement SystemVerilog RTL, and deliver
synthesis/timing clean design with constraints.
• Perform lint and clock domain crossing quality checks on the design.
• Work with with architects, other designers, verification teams, pre- and
post-silicon validation teams, synthesis, timing and back-end teams to
accomplish your tasks.
Requirements
• Bachelor's degree in Electrical Engineering or a related
field
• 5+ years in RTL design for SOC
• 5+ years of VLSI engineering
• 5+ years with code quality tools including: Spyglass, LINT, or CDC
• Are familiar with scripting in Python
• Are proficient with assertions
• Have good debug skills to analyze RTL test failures
• Have a "Learn and Be Curious" mindset
Nice-to-haves
• Master's degree or Ph.D. degree in Electrical Engineering or
related field
• Experience scripting for automation (e.g., Python, Perl, Ruby)
• Experience that includes strong analytical skills, attention to detail, and
effective communication abilities
• Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC
constraints
• Familiarity with data path design, interconnects, AXI protocol
Benefits
• Diverse Experiences
• Work/Life Balance
• Inclusive Team Culture
• Mentorship & Career Growth
• medical
• financial
• other benefits
