Applicants in the County of Los Angeles: Qualified applications with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act.
Applicants in San Francisco: Qualified applications with arrest or conviction records will be considered for employment in accordance with the San Francisco Fair Chance Ordinance for Employers and the California Fair Chance Act.
In accordance with Washington state law, we are highlighting our comprehensive benefits package, which is available to all eligible US based employees. Benefits for this role include:
Health, dental, vision, life, disability insurance
Retirement Benefits: 401(k) with company match
Paid Time Off: 20 days of vacation per year, accruing at a rate of 6.15 hours per pay period for the first five years of employment
Sick Time: 40 hours/year (statutory, where applicable); 5 days/event (discretionary)
Maternity Leave (Short-Term Disability + Baby Bonding): 28-30 weeks
Baby Bonding Leave: 18 weeks
Holidays: 13 paid days per year
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Cambridge, MA, USA; San Francisco, CA, USA; Mountain View, CA, USA; Goleta, CA, USA; Los Angeles, CA, USA; Seattle, WA, USA.Minimum qualifications:
• Master's degree in Electrical Engineering, Physics, related engineering discipline, or equivalent practical experience.
• Experience in superconductor logic families (e.g., RSFQ, ERSFQ, RQL, HFQ, AQFP).
• Experience performing tape-out of a superconducting IC chip.
• One or more published research paper or presentation at a relevant scientific conference.
Preferred qualifications:
• PhD in physics, electrical engineering, or a related engineering discipline.
• 7 years of research/industry experience in the design and simulation of superconductor digital logic circuits with 3 years of experience leading an Research and Development (R&D) group towards tape-out and demonstration of superconducting IC chips.
• Experience with full digital design flow including RTL, synthesis, verification, timing closure, place-and-route, and post-fabrication validation.
• Experience with low-temperature measurements of superconductor digital logic circuits.
• Experience with superconducting qubits.
• Proficiency with computer-aided design tools and electromagnetic simulation tools.
About The Job
As a Research Scientist, your primary focus will be designing and simulating superconductor digital logic circuits (such as single flux quantum (SFQ) logic and adiabatic quantum flux parametron (AQFP) logic) for qubit control and readout. You will engage in co-design loops with qubit designers and superconducting digital circuit designers, utilizing advanced IC design tools, numerical circuit simulation techniques and 3D electromagnetic modeling to optimize signal integrity, minimize crosstalk, manage thermal budgets, and aim performance metrics required for coherent control of qubits. You will also interface with fabrication engineers to help define and establish robust IC design standards that are compatible for both the sensitive superconducting qubits and the co-located cryogenic control electronics. This work is critical to building a fully integrated, modular chip stack that combines superconducting qubits with their control electronics directly within the cryogenic environment, accelerating the path toward large-scale, error-corrected quantum computer.
This work is critical to building a fully integrated, modular chip stack that combines superconducting qubits with their control electronics directly within the cryogenic environment, accelerating the path toward large-scale, error-corrected quantum computers.
The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications.
The US base salary range for this full-time position is $166,000-$244,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities
• Design and simulate superconductor digital logic circuits (such as single flux quantum (SFQ) logic, adiabatic quantum flux parametron (AQFP) logic, and other emerging superconductor logic families) for generating waveforms tailored to qubit control and readout.
• Develop superconductor digital logic systems enabling multiplexed qubit control and readout.
• Address issues in the integration of superconductor digital electronics such as multi-layer cell design, full-chip clock synchronization, flux trapping, and signal integrity.
• Collaborate with teams focused on design, fabrication, and measurement to validate fully integrated quantum processors.
• Publish research papers and present at leading scientific conferences to advance the state of the art and enhance publicity.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
