Duties
• Implement basicDFT schemes, including scan insertion, boundary scan, Mem BIST, DRC
clean,ATPG and pattern simulation,
• Support ATE bring-up, and debug the ATE patterns for production flow,
• Support logic BIST, Memory BIST diagnosisfor yield improvement.
Requirements
• Master degree or above in Electronic Engineering.
• Good understanding of synthesis and timing.
• Good understanding of IPs, integration and verification.
• Team spirit and strong communication skills.
• Enjoy challenging work and a Self-motivated good team player.
• Good programming in Perl, TCL and Shell programming is preferred.
• Hand-on experience in Synopsys (DFT Compiler/TetraMax) or Mentor Tessent is preferred.
• Good understanding of microprocessors, and computer system architecture is preferred
