Position: Hybrid Design Verification Engineer (UVM/SystemVerilog)
A leading semiconductor manufacturer is seeking a Design Verification Engineer in Vancouver. This role requires expertise in digital design and verification, including duties such as writing test plans, developing test benches using System Verilog/UVM, and providing technical leadership. Candidates should possess a relevant degree and experience in ASIC design and related tools. This position offers a hybrid work environment and focuses on innovative engineering solutions within the semiconductor industry.
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